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16-Bit, 100 kSPS PulSAR ADC in MSOP/QFN AD7683
FEATURES
16-bit resolution with no missing codes Throughput: 100 kSPS INL: 1 LSB typ, 3 LSB max Pseudodifferential analog input range 0 V to VREF with VREF up to VDD Single-supply operation: 2.7 V to 5.5 V Serial interface SPI(R)/QSPITM/MICROWIRETM/DSP-compatible Power dissipation : 4 mW @ 5 V, 1.5 mW @ 2.7 V, 150 W @ 2.7 V/10 kSPS Standby current: 1 nA 8-lead package: MSOP package and 3 mm x 3 mm QFN1 (LFCSP) (SOT-23 size) Improved 2nd source to ADS8320 and ADS8325
APPLICATION DIAGRAM
0.5V TO VDD 2.7V TO 5.5V
0 TO VREF +IN -IN
REF
VDD DCLOCK 3-WIRE SPI INTERFACE
04301-001
AD7683
GND
DOUT CS
Figure 1.
Table 1. MSOP, QFN (LFCSP)/SOT-23, 16-Bit PulSAR ADC
Type True Differential Pseudo Differential/Unipolar Unipolar 100 kSPS AD7684 AD7683 AD7680 250 kSPS AD7687 AD7685 AD7694 500 kSPS AD7688 AD7686
APPLICATIONS
Battery-powered equipment Data acquisition Instrumentation Medical instruments Process control
GENERAL DESCRIPTION
The AD7683 is a 16-bit, charge redistribution, successive approximation, PulSARTM analog-to-digital converter (ADC) that operates from a single power supply, VDD, between 2.7 V to 5.5 V. It contains a low power, high speed, 16-bit sampling ADC with no missing codes (B grade), an internal conversion clock, and a serial, SPI-compatible interface port. The part also contains a low noise, wide bandwidth, short aperture delay, track-and-hold circuit. On the CS falling edge, it samples an analog input, +IN, between 0 V to REF with respect to a ground sense, -IN. The reference voltage, REF, is applied externally and can be set up to the supply voltage. Its power scales linearly with throughput. The AD7683 is housed in an 8-lead MSOP or an 8-lead QFN (LFCSP) package, with an operating temperature specified from -40C to +85C.
1
QFN package in development. Contact factory for samples and availability.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD7683 TABLE OF CONTENTS
Specifications..................................................................................... 3 Timing Specifications....................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution.................................................................................. 6 Pin Configuration and Functional Descriptions.......................... 7 Terminology ...................................................................................... 8 Typical Performance Characteristics ............................................. 9 Application Information................................................................ 12 Circuit Information.................................................................... 12 Converter Operation.................................................................. 12 Transfer Functions...................................................................... 12 Typical Connection Diagram ................................................... 13 Analog Input ............................................................................... 13 Driver Amplifier Choice............................................................ 13 Voltage Reference Input ............................................................ 14 Power Supply............................................................................... 14 Digital Interface.......................................................................... 14 Layout .......................................................................................... 14 Evaluating the AD7683's Performance .................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15
REVISION HISTORY
9/04--Initial Version: Revision 0
Rev. 0 | Page 2 of 16
AD7683 SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = VDD; TA = -40C to +85C, unless otherwise noted. Table 2.
Parameter RESOLUTION ANALOG INPUT Voltage Range Absolute Input Voltage Analog Input CMRR Leakage Current at 25C Input Impedance THROUGHPUT SPEED Complete Cycle Throughput Rate DCLOCK Frequency REFERENCE Voltage Range Load Current DIGITAL INPUTS Logic Levels VIL VIH IIL IIH Input Capacitance DIGITAL OUTPUTS Data Format VOH VOL POWER SUPPLIES VDD VDD Range1 Operating Current VDD Standby Current2, 3 Power Dissipation Conditions Min 16 0 -0.1 -0.1 AD7683 All Grades Typ Max Unit Bits V V V dB nA
+IN - (-IN) +IN -IN fIN = 100 kHz Acquisition phase
VREF VDD + 0.1 0.1 65 1 See the Analog Input section. 10 100 2.9 VDD + 0.3 50
0 0 0.5 100 kSPS, V+IN - V-IN = VREF/2 = 2.5 V
S kSPS MHz V A
-0.3 0.7 x VDD -1 -1 5
0.3 x VDD VDD + 0.3 +1 +1
V V A A pF
ISOURCE = -500 A ISINK = +500 A Specified performance 100 kSPS throughput VDD = 5 V VDD = 2.7 V VDD = 5 V, 25C VDD = 5 V VDD = 2.7 V VDD = 2.7 V, 10 kSPS throughput TMIN to TMAX
Serial, 16 bits straight binary. VDD - 0.3 0.4 2.7 2.0 800 560 1 4 1.5 150 -40 5.5 5.5
V V V V A A nA mW mW W C
50 6
2
TEMPERATURE RANGE Specified Performance
+85
1 2
See the Typical Performance Characteristics section for more information. With all digital inputs forced to VDD or GND, as required. 3 During acquisition phase.
Rev. 0 | Page 3 of 16
AD7683
VDD = 5 V; VREF = VDD; TA = -40C to +85C, unless otherwise noted. Table 3.
Parameter ACCURACY No Missing Codes Integral Linearity Error Transition Noise Gain Error1, TMIN to TMAX Gain Error Temperature Drift Offset Error1, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Effective Number of Bits Conditions Min 15 -6 A Grade Typ Max Min 16 -3 B Grade Typ Max Unit Bits LSB LSB LSB ppm/C mV ppm/C LSB dB2 dB dB dB Bits
VDD = 5 V 5% fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz
3 0.5 2 0.3 0.7 0.3 0.05 90 -100 -100 90 14.7
+6 24 1.6
1 0.5 2 0.3 0.4 0.3 0.05 91 -108 -106 91 14.8
+3 15 1.6
88
88
1 2
See the Terminology section. These specifications include full temperature range variation, but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
VDD = 2.7 V; VREF = 2.5V; TA = -40C to +85C, unless otherwise noted. Table 4.
Parameter ACCURACY No Missing Codes Integral Linearity Error Transition Noise Gain Error1, TMIN to TMAX Gain Error Temperature Drift Offset Error1, TMIN to TMAX Offset Temperature Drift Power Supply Sensitivity AC ACCURACY Signal-to-Noise Spurious-Free Dynamic Range Total Harmonic Distortion Signal-to-(Noise + Distortion) Effective Number of Bits Conditions Min 15 -6 A Grade Typ Max Min 16 -3 B Grade Typ Max Unit Bits LSB LSB LSB ppm/C mV ppm/C LSB dB2 dB dB dB Bits
VDD = 2.7 V 5% fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz fIN = 1 kHz
3 0.85 2 0.3 0.7 0.3 0.05 85 -96 -94 85 13.8
+6 30 3.5
1 0.85 2 0.3 0.7 0.3 0.05 86 -100 -98 86 14
+3 15 3.5
1 2
See the Terminology section. These specifications do include full temperature range variation, but do not include the error contribution from the external reference. All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
Rev. 0 | Page 4 of 16
AD7683 TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; TA = -40C to +85C, unless otherwise noted. Table 5.
Parameter Throughput Rate CS Falling to DCLOCK Low CS Falling to DCLOCK Rising DCLOCK Falling to Data Remains Valid CS Rising Edge to DOUT High Impedance DCLOCK Falling to Data Valid Acquisition Time DOUT Fall Time DOUT Rise Time Symbol tCYC tCSD tSUCS tHDO tDIS tEN tACQ tF tR Min Typ Max 100 0 Unit kHz s ns ns ns ns ns ns ns
20 5
16 14 16 11 11
100 50 25 25
400
tCYC
CS
COMPLETE CYCLE
tSUCS
POWER DOWN DCLOCK
1 4 5
tACQ
tCSD
DOUT
Hi-Z 0
tEN
tHDO
D8 D7 D6 D5 D4 D3 D2 D1 D0
0
tDIS
Hi-Z
D15 D14 D13 D12 D11 D10 D9
Figure 2. Serial Interface Timing
Rev. 0 | Page 5 of 16
04301-002
(MSB) (LSB) NOTE: A MINIMUM OF 22 CLOCK CYCLES ARE REQUIRED FOR 16-BIT CONVERSION. SHOWN ARE 24 CLOCK CYCLES. DOUT GOES LOW ON THE DCLOCK FALLING EDGE FOLLOWING THE LSB READING.
AD7683 ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter Analog Inputs +IN1, -IN1 REF Supply Voltages VDD to GND Digital Inputs to GND Digital Outputs to GND Storage Temperature Range Junction Temperature JA Thermal Impedance JC Thermal Impedance Lead Temperature Range Vapor Phase (60 sec) Infrared (15 sec) Rating GND - 0.3 V to VDD + 0.3 V or 130 mA GND - 0.3 V to VDD + 0.3 V -0.3 V to +6 V -0.3 V to VDD + 0.3 V -0.3 V to VDD + 0.3 V -65C to +150C 150C 200C/W (MSOP-8) 44C/W (MSOP-8) 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
See the Analog Input section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
500A
IOL
TO DOUT
1.4V CL 100pF 500A IOH
04301-003
Figure 3. Load Circuit for Digital Interface Timing
2V 0.8V
tDELAY
2V 0.8V
tDELAY
2V 0.8V
04301-004
Figure 4. Voltage Reference Levels for Timing
90% DOUT
04301-006
10%
tR
tF
Figure 5. DOUT Rise and Fall Timing
Rev. 0 | Page 6 of 16
AD7683 PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
REF 1 +IN 2 -IN 3 GND 4
8
VDD DCLOCK
04301-005
AD7683
TOP VIEW (Not to Scale)
7 6 5
DOUT CS
Figure 6. 8-Lead MSOP and QFN1 (LFCSP) Pin Configuration
Table 7. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic REF +IN -IN GND CS DOUT DCLOCK VDD Type2 AI AI AI P DI DO DI P Function Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This pin should be decoupled closely to the pin with a ceramic capacitor of a few F. Analog Input. It is referred to in -IN. The voltage range, i.e., the difference between +IN and -IN, is 0 V to VREF. Analog Input Ground Sense. To be connected to the analog ground plane or to a remote sense ground. Power Supply Ground. Chip Select Input. On its falling edge, it initiates the conversions. The part returns in shutdown mode as soon as the conversion is done. It also enables DOUT. When high, DOUT is high impedance. Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK. Serial Data Clock Input. Power Supply.
1 2
QFN package in development. Contact factory for samples and availability. AI = Analog Input; DI = Digital Input; DO = Digital Output; and P = Power
Rev. 0 | Page 7 of 16
AD7683 TERMINOLOGY
Integral Nonlinearity Error (INL) Linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 11/2 LSB beyond the last code transition. The deviation is measured from the middle of each code to the true straight line (see Figure 21). Differential Nonlinearity Error (DNL) In an ideal ADC, code transitions are 1 LSB apart. DNL is the maximum deviation from this ideal value. It is often specified in terms of resolution for which no missing codes are guaranteed. Offset Error The first transition should occur at a level 1/2 LSB above analog ground (38.1 V for the 0 V to 5 V range). The offset error is the deviation of the actual transition from that point. Gain Error The last transition (from 111...10 to 111...11) should occur for an analog voltage 11/2 LSB below the nominal full scale (4.999886 V for the 0 V to 5 V range). The gain error is the deviation of the actual level of the last transition from the ideal level after the offset has been adjusted out. Spurious-Free Dynamic Range (SFDR) The difference, in decibels (dB), between the rms amplitude of the input signal and the peak spurious signal. Effective Number of Bits (ENOB) ENOB is a measurement of the resolution with a sine wave input. It is related to S/(N+D) by the following formula
ENOB = (S /[N + D]dB - 1.76) / 6.02
and is expressed in bits. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in dB. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding harmonics and dc. The value for SNR is expressed in dB. Signal-to-(Noise + Distortion) Ratio (S/[N+D]) S/(N+D) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/(N+D) is expressed in dB. Aperture Delay Aperture delay is a measure of the acquisition performance and is the time between the falling edge of the CS input and when the input signal is held for a conversion. Transient Response The time required for the ADC to accurately acquire its input after a full-scale step function was applied.
Rev. 0 | Page 8 of 16
AD7683 TYPICAL PERFORMANCE CHARACTERISTICS
3 POSITIVE INL = +0.43LSB NEGATIVE INL = -0.97LSB 2 2 3 POSITIVE DNL = +0.43LSB NEGATIVE DNL = -0.41LSB
1
DNL (LSB)
04301-011
1
INL (LSB)
0
0
-1
-1
-2
-2
04301-011
-3 0 16384 32768 CODE 49152
-3 0 16384 32768 CODE 49152
65536
65536
Figure 7. Integral Nonlinearity vs. Code
Figure 10. Differential Nonlinearity vs. Code
7000 62564 6000 5000 VDD = REF = 2.5V
120000 102287 100000 VDD = REF = 5V
80000
COUNTS
35528
COUNTS
4000 3000 25440 2000 1000 0 0 1 50 2755
60000
40000
20000
04301-009
15152 0 0 6
4604 130 0 0
8 0 0 0 7A0E 7A0F 7A10 7A11 7A12 7A13 7A14 7A15 7A16 CODE IN HEX
0
79FD 79FE 79FF 7A00 7A01 7A02 7A03 7A04 7A05 7A06 7A07 7A08
CODE IN HEX
Figure 8. Histogram of a DC Input at the Code Center
Figure 11. Histogram of a DC Input at the Code Center
0 -20 16384 POINT FFT VDD = REF = 5V fS = 100kSPS fIN = 20.43kHz SNR = 92.7dB THD = -105.7dB SFDR = -106.4dB
0 -20 16384 POINT FFT VDD = REF = 2.5V fS = 100kSPS fIN = 20.43kHz SNR = 88.7dB THD = -102.6dB SFDR = -104.6dB
AMPLITUDE (dB OF FULL SCALE)
-40 -60 -80 -100 -120 -140
AMPLITUDE (dB OF FULL SCALE)
-40 -60 -80 -100 -120 -140 -160 -180 0 10 20 30 FREQUENCY (kHz)
04301-008
-160 -180 0 10 20 30 FREQUENCY (kHz) 40 50
40
50
Figure 9. FFT Plot
Figure 12. FFT Plot
Rev. 0 | Page 9 of 16
04301-007
04301-010
13619
AD7683
100 17 1200
fS = 100kSPS
1000 95
SNR, S/[N+D] (dB)
SNR
16
OPERATING CURRENT (A)
800
90 S/[N+D] ENOB 85
15
ENOB (Bits)
600
400
14
04301-013
200
04301-017
80 2.0
2.5
3.0 3.5 4.0 4.5 REFERENCE VOLTAGE (V)
5.0
13 5.5
0 2.0
2.5
3.0
3.5 4.0 SUPPLY (V)
4.5
5.0
5.5
Figure 13. SNR, S/(N + D), and ENOB vs. Reference Voltage
Figure 16. Operating Current vs. Supply
100
900 VDD = 5V, fS = 100kSPS 800
95
90
S/[N+D] (dB)
OPERATING CURRENT (A)
VREF = 5V, -10dB
700 600 500 400 300 200 100 0 -55
04301-018
VREF = 5V, -1dB 85 VREF = 2.5V, -1dB 80
VDD = 2.7V, fS = 100kSPS
75
04301-014
70 0 50 100 FREQUENCY (kHz) 150 200
-34
-15
5 25 45 65 TEMPERATURE (C)
85
105
125
Figure 14. S/[N + D] vs. Frequency
Figure 17. Operating Current vs. Temperature
-80
1000
-85 VREF 2.5V = -1dB -90
POWER-DOWN CURRENT (nA) 750
THD (dB)
-95 VREF 5V = -1dB -100
500
250
04301-019
-105
04301-015
-110 0 40 80 120 FREQUENCY (kHz) 160 200
0 -55
-35
-15
5 25 45 65 TEMPERATURE (C)
85
105
125
Figure 15. THD, ENOB vs. Frequency
Figure 18. Power-Down Current vs. Temperature
Rev. 0 | Page 10 of 16
AD7683
6 5 4
OFFSET, GAIN ERROR (LSB)
3 2 1 0 -1 -2 -3 -4 -5 -6 -55 -35 -15 5 25 45 65 TEMPERATURE (C) 85 105 125
04301-016
OFFSET ERROR
GAIN ERROR
Figure 19. Offset and Gain Error vs. Temperature
Rev. 0 | Page 11 of 16
AD7683 APPLICATION INFORMATION
+IN SWITCHES CONTROL MSB 32,768C 16,384C REF COMP GND 32,768C 16,384C MSB 4C 2C C C LSB SW- CNV
04301-020
LSB 4C 2C C C
SW+ BUSY CONTROL LOGIC OUTPUT CODE
-IN
Figure 20. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7683 is a low power, single-supply, 16-bit ADC using a successive approximation architecture. The AD7683 is capable of converting 100,000 samples per second (100 kSPS) and powers down between conversions. When operating at 10 kSPS, for example, it consumes typically 150 W with a 2.7 V supply, ideal for battery-powered applications. The AD7683 provides the user with an on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple, multiplexed channel applications. The AD7683 is specified from 2.7 V to 5.5 V. It is housed in a 8-lead MSOP package or a tiny, 8-lead QFN (LFCSP) package. The AD7683 is an improved second source to the ADS8320 and ADS8325. For even better performance, consider the AD7685.
array between GND and REF, the comparator input varies by binary-weighted voltage steps (VREF/2, VREF/4...VREF/65536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code.
TRANSFER FUNCTIONS
The ideal transfer function for the AD7683 is shown in Figure 21 and Table 8.
ADC CODE (STRAIGHT BINARY)
111...111 111...110 111...101
CONVERTER OPERATION
The AD7683 is a successive approximation ADC based on a charge redistribution DAC. Figure 20 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary-weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator's input are connected to GND via SW+ and SW-. All independent switches are connected to the analog inputs. Thus, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the +IN and -IN inputs. When the acquisition phase is complete and the CS input goes low, a conversion phase is initiated. When the conversion phase begins, SW+ and SW- are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the inputs, +IN and -IN, captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor
000...010 000...001 000...000 -FS
-FS + 1 LSB
-FS + 0.5 LSB
ANALOG INPUT
Figure 21. ADC Ideal Transfer Function
Table 8. Output Codes and Ideal Input Voltages
Description FSR - 1 LSB Midscale + 1 LSB Midscale Midscale - 1 LSB -FSR + 1 LSB -FSR Analog Input VREF = 5 V 4.999924 V 2.500076 V 2.5 V 2.499924 V 76.3 V 0V Digital Output Code Hexadecimal FFFF1 8001 8000 7FFF 0001 00002
1
2
This is also the code for an overranged analog input (V+IN - V-IN above VREF - VGND). This is also the code for an underranged analog input (V+IN - V-IN below VGND).
Rev. 0 | Page 12 of 16
04301-021
+FS - 1 LSB +FS - 1.5 LSB
AD7683
(NOTE 1) REF 2.2 TO 10F (NOTE 2) 100nF 2.7V TO 5.25V
33 0 TO VREF (NOTE 3) 2.7nF (NOTE 4)
REF +IN
VDD DCLOCK
AD7683
-IN GND
DOUT CS
3-WIRE INTERFACE
Figure 22. Typical Application Diagram
TYPICAL CONNECTION DIAGRAM
Figure 22 shows an example of the recommended application diagram for the AD7683.
sampling capacitor. During the conversion phase, where the switches are opened, the input impedance is limited to CPIN. RIN and CIN make a 1-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise. When the source impedance of the driving circuit is low, the AD7683 can be driven directly. Large source impedances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance.
ANALOG INPUT
Figure 23 shows an equivalent circuit of the input structure of the AD7683. The two diodes, D1 and D2, provide ESD protection for the analog inputs, +IN and -IN. Care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V, because this will cause these diodes to become forward-biased and start conducting current. However, these diodes can handle a forward-biased current of 130 mA maximum. For instance, these conditions could eventually occur when the input buffer's (U1) supplies are different from VDD. In such a case, an input buffer with a short-circuit current limitation can be used to protect the part.
VDD D1 CPIN GND CIN
DRIVER AMPLIFIER CHOICE
Although the AD7683 is easy to drive, the driver amplifier needs to meet the following requirements: * The noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the SNR and transition noise performance of the AD7683. Note that the AD7683 has a noise much lower than most other 16-bit ADCs and, therefore, can be driven by a noisier op amp while preserving the same or better system performance. The noise coming from the driver is filtered by the AD7683 analog input circuit 1-pole, low-pass filter made by RIN and CIN or by the external filter, if one is used. For ac applications, the driver needs to have a THD performance suitable to that of the AD7683. Figure 15 shows the THD versus frequency that the driver should exceed. For multichannel multiplexed applications, the driver amplifier and the AD7683 analog input circuit must be able to settle for a full-scale step of the capacitor array at a 16-bit level (0.0015%). In the amplifier's data sheet, settling at 0.1% to 0.01% is more commonly specified. This could differ significantly from the settling time at a 16-bit level and should be verified prior to driver selection.
+IN OR -IN
RIN
D2
04301-023
*
Figure 23. Equivalent Analog Input Circuit
This analog input structure allows the sampling of the differential signal between +IN and -IN. By using this differential input, small signals common to both inputs are rejected. For instance, by using -IN to sense a remote signal ground, ground potential differences between the sensor and the local ADC ground are eliminated. During the acquisition phase, the impedance of the analog input +IN can be modeled as a parallel combination of the capacitor CPIN and the network formed by the series connection of RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically 600 and is a lumped component made up of some serial resistors and the on-resistance of the switches. CIN is typically 30 pF and is mainly the ADC
*
Rev. 0 | Page 13 of 16
04301-022
NOTE 1: SEE REFERENCE SECTION FOR REFERENCE SELECTION. NOTE 2: CREF IS USUALLY A 10F CERAMIC CAPACITOR (X5R). NOTE 3: SEE DRIVER AMPLIFIER CHOICE SECTION. NOTE 4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
AD7683
Table 9. Recommended Driver Amplifiers
Amplifier AD8021 AD8022 OP184 AD8605, AD8615 AD8519 AD8031 Typical Application Very low noise and high frequency Low noise and high frequency Low power, low noise, and low frequency 5 V single-supply, low power Small, low power, and low frequency High frequency and low power
A falling edge on CS initiates a conversion and the data transfer. After the fifth DCLOCK falling edge, DOUT is enabled and forced low. The data bits are then clocked, MSB first, by subsequent DCLOCK falling edges. The data is valid on both SCK edges. Although the rising edge can be used to capture the data, a digital host also using the SCK falling edge allows a faster reading rate, provided it has an acceptable hold time.
CONVERT
VOLTAGE REFERENCE INPUT
The AD7683 voltage reference input, REF, has a dynamic input impedance. It should therefore be driven by a low impedance source with efficient decoupling between the REF and GND pins, as explained in the Layout section. When REF is driven by a very low impedance source (e.g., an unbuffered reference voltage like the low temperature drift ADR43x reference or a reference buffer using the AD8031 or the AD8605), a 10 F (X5R, 0805 size) ceramic chip capacitor is appropriate for optimum performance. If desired, smaller reference decoupling capacitor values down to 2.2 F can be used with a minimal impact on performance, especially DNL.
CS
DIGITAL HOST
DOUT DATA IN
04301-025
AD7683
DCLOCK
CLK
Figure 25. Connection Diagram
LAYOUT
The printed circuit board housing the AD7683 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7683 with all its analog signals on the left side and all its digital signals on the right side eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7683 is used as a shield. Fast switching signals, such as CS or clocks, should never run near analog signal paths. Crossover of digital and analog signals should be avoided. At least one ground plane should be used. It could be common or split between the digital and analog section. In such a case, it should be joined underneath the AD7683. The AD7683 voltage reference input REF has a dynamic input impedance and should be decoupled with minimal parasitic inductances. That is done by placing the reference decoupling ceramic capacitor close to, and ideally right up against, the REF and GND pins and by connecting these pins with wide, low impedance traces. Finally, the power supply, VDD, of the AD7683 should be decoupled with a ceramic capacitor, typically 100 nF, and placed close to the AD7683. It should be connected using short and large traces to provide low impedance paths and reduce the effect of glitches on the power supply lines.
POWER SUPPLY
The AD7683 powers down automatically at the end of each conversion phase and, therefore, the power scales linearly with the sampling rate, as shown in Figure 24. This makes the part ideal for low sampling rates (even of a few Hz) and low batterypowered applications.
1000
100
OPERATING CURRENT (A)
VDD = 5V
10
VDD = 2.7V
1
0.1
04301-024
0.01 10
100
1k SAMPLING RATE (SPS)
10k
100k
EVALUATING THE AD7683'S PERFORMANCE
Other recommended layouts for the AD7683 are outlined in the evaluation board for the AD7683 (EVAL-AD7683). The evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-CONTROL BRD2.
Figure 24. Operating Current vs. Sampling Rate
DIGITAL INTERFACE
The AD7683 is compatible with SPI, QSPI, digital hosts, and DSPs (e.g., Blackfin(R) ADSP-BF53x or ADSP-219x). The connection diagram is shown in Figure 25 and the corresponding timing is given in Figure 2.
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AD7683 OUTLINE DIMENSIONS
3.00 BSC
8 5
3.00 BSC
4
4.90 BSC
PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.15 0.00 0.38 0.22 COPLANARITY 0.10
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 26. 8-Lead Micro Small Outline Package [MSOP] (RM-8) Dimensions Shown in Millimeters
INDEX AREA
3.00 BSC SQ
8
PIN 1 INDICATOR
1
1.50 BCS SQ
TOP VIEW
0.65 BSC
EXPOSED PAD
(BOTTOM VIEW)
2.48 2.38 2.23
4
5
0.80 0.75 0.70
0.80 MAX 0.55 TYP
SIDE VIEW
0.50 0.40 0.30 0.05 MAX 0.02 NOM 0.20 REF
1.74 1.64 1.49
PADDLE CONNECTED TO GND. THIS CONNECTION IS NOT REQUIRED TO MEET THE ELECTRICAL PERFORMANCES
SEATING PLANE
0.30 0.23 0.18
Figure 27. 8-Terminal Quad Flat No Lead Package[QFN1 (LFCSP)] 3 mm x 3 mm Body (CP-8-9) Dimensions Shown in Millimeters
ORDERING GUIDE
Models AD7683ARM AD7683ARMRL7 AD7683BRM AD7683BRMRL7 EVAL-AD7683CB2 EVAL-CONTROL BRD23 EVAL-CONTROL BRD33 Integral Nonlinearity 6 LSB max 6 LSB max 3 LSB max 3 LSB max Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C Package (Option) MSOP (RM-8) MSOP (RM-8) MSOP (RM-8) MSOP (RM-8) Evaluation Board Controller Board Controller Board Transport Media, Quantity Tube, 50 Reel, 1,000 Tube, 50 Reel, 1,000 Branding C1L C1L C1C C1C
1 2
QFN package in development. Contact factory for samples and availability. This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRDx for evaluation/demonstration purposes. 3 These boards allow a PC to control and communicate with all Analog Devices' evaluation boards ending in the CB designators.
Rev. 0 | Page 15 of 16
AD7683 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04301-0-9/04(0)
Rev. 0 | Page 16 of 16

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